Low-Power CMOS Ramp Generator Circuit for DC-DC Converters

Ramp-signal generators are particularly critical in controlling the frequency and dutycycle of pulse-width modulated (PWM) switching supplies. They are normally implemented with a timed charging current source into a capacitor and a reset switch controlled by two comparators whose reference signals set the lower and upper limits of the ramp. A fast comparator is required to ensure the reset operation is short and therefore mitigate its adverse effects on switching supply frequency. Unfortunately, the resulting delay requirements of the comparator are often stringent and difficult to meet under low power conditions. To alleviate the comparator’s bandwidth requirement, a scheme is proposed by which the circuit generates a non-ideal ramp with its reset time to be 10% of period utilizing the fact that the ramp signal is needed in DC-DC converter’s controller feedback loop only until the duty-cycle is set. Therefore, the condition on comparator delay and its respective power is relaxed. The proposed scheme was experimentally verified with a 770 kHz ramp generator prototype embedded in a current-mode controller buck DC-DC converter built in a 0.5-μm CMOS process, which achieved 28 mV amplitude accuracy with current consumption of 256 μA.